1. Field of the Invention
The present invention relates to a bidirectional socket stimulus interface for a logic simulator, and more particularly, to a bidirectional socket stimulus interface which allows input stimuli to be provided interactively from a keyboard, from a data file, or from a UNIX(copyright) socket directly to the logic simulator. The system of the invention also allows the user to provide input stimuli which behaviorally model complex logic systems that the logic simulator model is part of by basing the state of the next input vector on the present state of the logic simulator.
2. Description of the Prior Art
When designing integrated circuits for performing particular functions, design engineers have traditionally drawn schematic diagrams of the proposed circuit setting forth all of the elements and interconnections necessary for the circuit to perform the desired functions. From the schematic diagrams, prototype circuits were built and tested. Before the advent of computer aided design (CAD) systems, the prototype of the circuit was actually built using techniques such as wire-wrapping and the like. The resulting prototype circuit was then tested by applying different combinations of input signals (input vectors) to the circuit and checking the output of the circuit on a device such as an oscilloscope. Errors in the circuit design were found when the outputs were not those desired, and the design flaw or improper connection was typically manually tracked down by careful examination of the circuit schematic and prototype wiring. Once the design flaw or improper connection was found, the prototype circuit was rebuilt and retested. This circuit design process was very time-consuming and tedious, and accordingly, design engineers sought different methods for converting the circuit schematic into a circuit which performs the desired functions.
Computer aided design (CAD) systems have greatly helped design engineers in this circuit design process. CAD systems allow the design engineer to prepare the circuit schematics on the computer, to lay out the circuit for implementation on a circuit board, and to test the circuit using logic simulation techniques. Logic simulators thus allow the design engineer to test the proposed circuit design without actually building the prototype. This is accomplished by having the design engineer specify as input to the logic simulator the elements and nodes of the circuit and the signals expected at those nodes for particular inputs. This information is determined directly from the circuit schematic diagram and is typically input into the logic simulator as an input file. The logic simulator runs this data through a model of the proposed circuit to generate the outputs of the simulated circuit. Such logic simulators are limited, however, in that they do not provide for use of a behavioral model which characterizes the circuit and thus do not allow the simulation input vectors for testing the circuit design to be automatically extracted from the circuit schematic diagram. Instead, the design engineer has had to painstakingly design and implement the simulation model and to create the input vector file.
An example of a logic simulator of the type described above is shown in FIG. 1. As shown, a simulation model 100 of the circuit being tested is provided to a logic simulator, such as a switch-level logic simulator 102, which simulates the functions of the circuit represented by the simulation model 100. Switch-level logic simulator 102 may include node evaluation algorithms which make it possible for the logic simulator 102 to simulate operation of circuits modeled entirely with bidirectional switches. Switch-level logic simulators are thus important tools for circuit design, for whenever a design engineer stops using classic logic gates and starts using dynamic or transfer gate logic, a switch-level logic simulator becomes necessary. This is because a conventional logic simulator cannot model all of the complex interactions which take place between non-classical transistor connections. Accordingly, the description herein is directed towards a system including a switch-level logic simulator.
The simulation model 100 of the circuit must be generated by the design engineer before a simulation can take place. This means that all of the elements, interconnections and nodes for a circuit design must be gathered together and converted into an input data file which is in a format acceptable to the logic simulator 102. Typically, the input data file contains a file having one entry for every transistor in the design, where the file is described using node numbers only, and also includes a file containing the node number to signal name mapping. The model is generated by converting the input files into a binary database which can be loaded directly into the logic simulator 102. In other words, the logic simulator 102 reads the input data file and formats it into a memory based data structure that expresses the connectivity of the circuit model. This data structure is then stored as a file in the logic simulator 102 and is referred to as the logic simulator database.
In addition to the simulation model 100, it is necessary to generate an input vector file 104 of input stimuli so that operation of the circuit can be simulated. The input vector file 104 contains all of the desired input stimulus patterns (vectors) and logic simulator control commands. The input vector file 104 may also contain any output assertions that predict the desired behavior of the circuit. The inclusion of the output assertions in an input vector file 104 allows the input vector set to act as a regression test and greatly simplifies post-processing of a simulation run. In addition to input stimuli, known faults may be inserted into the input vector file 104 so that the logic simulator 102 may be used as a fault simulator.
When the logic simulator 102 is run, two output files are typically created. The first file is the simulator list file, while the second is the raw data file. The simulator list file is typically an ASCII file which lists any simulator generated status messages as well as any assertion failures. The raw data file, on the other hand, is typically a non-ASCII file which contains the node transitions for every node in the logic simulator model for all of the time steps in the simulation. The raw data files are used by the logic simulator post-processor to display any requested node for any time period. In particular, the post-processor translates the raw data file into a form which is viewable by the user. The user can preferably control which signals and which time steps are displayed.
In addition, the logic simulator 102 may include a file which contains the values of all the nodes at a particular point in time. This file can be used to reset a simulation to a known state and is commonly used when developing an input vector file to save a state of the simulation model, such as a reset state, which can be restored over and over throughout a simulation. The ability to restart at a known point makes the process of developing an input vector file 104 easier.
As part of the test vector creation and simulation techniques described above, design engineers wrote detailed behavioral descriptions of both the circuit and the outside world as test and circuit specific vectors. Previous simulation methodologies provided two methods of creating such circuit specific vectors. In the first method, the input vector file 104 is created by the design engineer by hand by specifying the input vectors necessary to excite the circuit in accordance with the truth table. In other words, the design engineer has had to specify the portions of the truth table of the circuit which was to be tested by a particular simulation and has had to prepare the necessary input file 104 taking into account the capacitances of the circuit, propagation delays and the like so that the simulation would perform correctly. This process requires trial and error on the part of the design engineer and requires the design engineer to assume the proper simulation output response for each input stimulus. In accordance with this method, vector creation is tedious, time-consuming and inflexible for the design engineer and makes simulation of complicated dependent systems difficult. On the other hand, the second method handles complicated dependent systems by modeling them with a high level behavioral language. This method removes the designer from the actual vectors, assumes the function of the circuit can be predicted and involves modeling the entire system including the circuit itself. However, this method takes a great deal of time to develop and debug since the input vectors must be checked by hand in accordance with the output assertions.
Accordingly, it is desired that the best of these two methodologies be combined so that an interactive simulation environment can be created which allows for simple functional models (or state machines) to interrogate the simulated circuit at each evaluation point based on predefined rules and to interactively stimulate the simulated circuit as necessary. The present invention has been designed to meet these needs by providing the flexibility of a rule based system at the simulator level.
The above-mentioned problems in the prior art have been overcome in accordance with the present invention by developing a simple simulation methodology which acts interactively with the logic simulator and in the end allows the circuit description to model the circuit while letting higher level language models represent the other parts of the system. This is accomplished in accordance with the present invention by using a sockets interface such as a ARPA/Berkeley UNTX(copyright) sockets interface to establish a communications socket between the logic simulator and a system for developing input stimuli based upon the state of the logic simulator. In other words, rather than predicting the response of the circuit being simulated and generating the input stimuli from the predicted response of the simulated circuit, the present invention allows the input stimuli to be determined directly from the actual state of the logic simulator. By so providing a communications socket and a real-time decision making capability based upon the output of the logic simulator, a functional simulation language for simulation in which the circuit description models the circuit and state machines model the world external to the circuit has been made possible in accordance with the invention. The present invention thus makes integrated circuit design and testing using CAD systems substantially easier for design engineers.
The system of the invention verifies the logical function of a circuit being designed by providing a communications interface from the logic simulator to a state based system which can model the external world, that is, the world external to the simulated circuit. Such a system in accordance with the present invention comprises a logic simulator (preferably a switch-level logic simulator), adaptive means for determining input vectors to the logic simulator and means for providing bidirectional communication between the logic simulator and the adaptive means. Generally, the logic simulator of the invention is responsive to input stimuli so as to perform a logic simulation which gives the logic values of nodes of the circuit being simulated in response to the Input stimuli. These input stimuli are provided by the adaptive means, which determines (based on simulated logic values of nodes of the simulated circuit as received from the logic simulator) input vectors representing the next input stimuli to the logic simulator for setting logic values of the nodes of the simulated circuit. The bidirectional communication means, on the other hand, provides bidirectional communication between the logic simulator and the adaptive means so as to provide current input stimuli to the logic simulator for a simulation and to provide the simulated logic values of the nodes of the simulated circuit to the adaptive means for use thereby in determining input vectors representing the next input stimuli.
Preferably, such a system in accordance with the invention comprises means for providing a program to the adaptive means, where the program includes state based equations which are processed by the adaptive means to determine input vectors representing the next input stimuli from the simulated logic values of the nodes of the simulated circuit resulting from application of the current input stimuli to the simulated circuit. For this purpose, the adaptive means preferably includes processing means for performing the steps of:
determining the next action requested by the program;
reading from the bidirectional communication means the current state of the logic simulator;
calculating the input vectors representing the next input stimuli from the current state of the logic simulator;
applying the input vectors representing the next input stimuli to the logic simulator via the bidirectional communication means;
advancing the logic simulator to its next state;
reading from the bidirectional communication means the simulated logic values of the nodes of the simulated circuit;
determining if the read simulated logic values of the nodes of the simulated circuit are correct; and
providing an indication to a user of the logic simulator whether the simulated logic values are correct.
On the other hand, the adaptive means could itself comprise a program including state based equations unique to the simulated circuit which are processed by the adaptive means to determine input vectors representing the next input stimuli from the simulated logic values of the nodes of the simulated circuit resulting from application of the current input stimuli to the simulated circuit. In such a case, the program could be hard-coded into a processor of the adaptive means.
Accordingly, the system of the invention provides an automated method of verifying the logical function of a simulated circuit using a logic simulator which is responsive to input stimuli to perform a logic simulation which gives the logic values of nodes of the simulated circuit. Such a method is characterized in that it includes the steps of reading the current state of the logic simulator and calculating the input vectors representing the next input stimuli from the current state of the logic simulator. Such state-based calculation of the input stimuli has not heretofore been possible. Such a method in accordance with the invention is further characterized by the steps of:
applying the input vectors representing the next input stimuli to the logic simulator;
advancing the logic simulator to its next state;
reading the simulated logic values of the nodes of the simulated circuit for the next state of the logic simulator;
determining if the read simulated logic values of the nodes of the simulated circuit are correct; and
providing an indication to a user of the logic simulator whether the simulated logic values are correct.
Accordingly, in accordance with the invention the logic simulator itself may be controlled through logic simulator directives included in an input vector file. Input stimuli can also be generated using high-level programming languages, thereby greatly simplifying the circuit design and testing process using CAD systems.